Not applicable.
Not applicable.
This invention relates generally to printed circuit boards and, more particularly, to multi-layer printed circuit boards which carry high speed signals.
As is known in the art, conductive traces are formed on printed circuit boards for carrying data and power signals between components mounted on the board. Space considerations often require the use of multi-layer printed circuit boards including multiple layered dielectric substrates with conductive traces formed on each substrate.
In a conventional printed circuit board manufacturing process, the printed circuit board is assembled using xe2x80x9claminate.xe2x80x9d Laminate is a thin sheet of a matrix material, usually epoxy, that is reinforced by fiberglass. A copper cladding is adhered to each side of the epoxy sheet. The epoxy is cured to hold the laminate together. The copper cladding is etched to make the circuit traces on each side of the laminate.
Several sheets of laminate are stacked up with dielectric spacers (sometimes called xe2x80x9cprepregxe2x80x9d) in between. The dielectric spacers provide the required separation between circuit traces on the opposing faces of adjacent laminates. The spacers also secure the laminates into a finished printed circuit board. The spacers are usually made of a partially cured resin. The stack of laminates and spacers are pressed together, usually in a heated oven, to force the resin from the spacers to adhere to the laminates and cure the entire stack into a rigid printed circuit board.
In order to interconnect conductive traces on different layers, conductive vias extend between layers of the multi-layer printed circuit board. For this purpose, conductive vias intersect vertically aligned pads joined to conductive traces on different layers. Conductive vias also interconnect components mounted on the board to conductive traces on inner layers of the board. More particularly, a contact of the component, such as a press-fit pin, makes contact with the conductive walls of the via and the conductive walls of the via, in turn, contact one or more pads of conductive traces on inner layers of the board. Vias which extend through all layers of a multi-layer board are sometimes referred to as through holes.
Conductive vias are formed after the layered substrates are formed into a board by drilling holes through at least a portion of the board and plating the walls of the holes with a conductive material, such as copper. Typically, a thin layer of copper is applied by an electroless process. An electrical potential is connected to this thin layer of copper and a thicker layer of copper is deposited over the thin layer by an electrolytic deposition process. In order to ensure reliable plating of the via walls, the aspect ratio of the printed circuit board thickness to the via diameter is typically below 14:1. For example, for a circuit board having a thickness on the order of 0.300xe2x80x3 (7 mm), the via diameter must be at least 0.22xe2x80x3 (0.5 mm). This minimum via diameter limits the number of vias that can be provided in a given circuit board area.
An illustrative multi-layer printed circuit board 10 having a conductive via 14 is shown in FIG. 1 to include dielectric layers 12a, 12b, and 12c, with conductive traces 16,18 formed on layers 12b, 12c, respectively. In the example, a four layer board is shown. It should be appreciated that the number of layers is selected for simplicity of illustration and the number of layers is not a limitation on the invention. However, the invention will be most useful with thicker boards or boards carrying high frequency signals. The signal integrity of boards carrying signals in excess of 2.5 GHz will be most improved by the invention. The conductive via 14 extends through a pad 17 of signal trace 16 and a pad 19 of signal trace 18 in order to electrically interconnect the signal traces 16 and 18. Also, a pin 26 of a component 28 inserted at least partially into the via 14 contacts the conductive walls of the via and thus, is electrically connected to signal traces 16, 18.
The high data rates of signals carried by printed circuit boards require careful attention to aspects of the circuit board structure affecting signal quality. As one example, portions of a via extending beyond inner layers of the board which are interconnected to other layers and/or to a component mounted on the board, such as portion 20 of via 14, can act as a resonant stub, causing undesirable signal reflections at certain frequencies.
One solution to this problem is to use xe2x80x9cblindxe2x80x9d or buried vias for interconnecting traces on inner layers of a printed circuit board. A blind via extends from a surface of a board through only a portion of the layers of a multi-layer printed circuit board. It is, however, undesirable to make blind vias of multiple depths. Buried vias are used to interconnect two interior layers of the printed circuit board. Buried vias are formed by first making a subassembly from several layers of the printed circuit board. A hole is drilled through these layers and the hole is plated. Additional substrate layers are added to the top and the bottom of the subassembly to make a completed printed circuit board. The resulting buried vias are inaccessible and increase the manufacturing complexity of the multi-layer printed circuit board.
An alternative technique for eliminating resonant stubs in conductive vias is to remove the stub portions of the via by drilling them out of the board. For example, by drilling a hole through layer 12c concentrically around, and with a larger diameter than the via 14, the via portion 20 extending through layer 12c is removed. However, this technique requires additional is manufacturing steps.
It is an object of the invention to eliminate or at least decrease the length of resonant stub portions of conductive vias in a multi-layer printed circuit board.
This and other objects of the invention are achieved by providing, in a preferred embodiment of a multi-layer printed circuit board, a via having an upper electrically conductive portion, a lower electrically conductive portion, and an intermediate, electrically insulating portion between the upper and lower portions. The electrically insulating portion provides a discontinuity in the conductive coating of the via. Thus, the via may be referred to as a xe2x80x9cdiscontinuous via.xe2x80x9d Both the upper and lower conductive portions of the via can be used to interconnect conductive traces on layers which are on the same side of the electrically insulating portion of the via and to interconnect components mounted on the board to conductive traces on inner layers of the board.
With this arrangement, portions of the via extending beyond the layers of the board which are interconnected by the via, which would otherwise form a resonant stub, are either shortened or eliminated. A further advantage of the discontinuous via is that two pins, from two different components, can be inserted into a single via, one into the upper conductive portion and one into the lower conductive portion. In this way, the circuit board density is increased.
The discontinuous via can be formed in various structures and by various fabrication techniques. In one embodiment, one or more entire layers of a multi-layer circuit board are comprised of a non-platable material and the intermediate insulating portion of the via extends through the non-platable layer. The material is xe2x80x9cnon-platablexe2x80x9d in the sense that a conductive coating applied to the via by an electroless plating process does not adhere to the material. One suitable non-platable material is a fluoropolymer resin, such as TEFLON(copyright) polytetrafluoroethylene (PTFE). In locations of the circuit board where it is desired to provide a conventional via with a continuously conductive coating through the board (i.e., a xe2x80x9ccontinuous viaxe2x80x9d), clearance holes formed in the non-platable layer are provided with a platable inner surface to form a platable xe2x80x9cplugxe2x80x9d, either by filling the hole with a platable material, such as epoxy resin, prior to drilling and plating the continuous via or by chemically conditioning the non-platable material to make it platable.
In an alternative embodiment, only portions of one or more of the circuit board layers are comprised of a non-platable material. For example, in a location where it is desired to provide a discontinuous via, a clearance hole is formed in a conventional dielectric circuit board layer and is filled with PTFE to form a xe2x80x9cnon-platable plug.xe2x80x9d The discontinuous via is formed by drilling a hole through the board, including through the non-platable plug, and plating the drilled hole. Since the plating does not adhere to the non-platable plug, a discontinuity in the via coating is provided. Alternatively, a layer which has only portions of non-platable material can formed by punching holes in a sheet of non-platable material and filling the voids with platable material.
According to a further embodiment, a discontinuous via is formed by drilling, through a multi-layer circuit board, a hole having a first portion of a first diameter, a second portion of a second diameter, and an intermediate portion between the first and second portions and having a third diameter smaller than the first and second diameters. This multi-diameter hole is formed by drilling a relatively small diameter hole through the board, drilling partially through the board from a first surface concentrically around the small diameter hole, and drilling partially through the board from the second, opposite surface concentrically around the small diameter hole. The hole is then plated and is further drilled with a drill bit having a diameter greater than the first diameter and less than the second and third diameters. This last drilling step removes the plating on the narrow diameter, intermediate portion of the via to provide a discontinuity in the via coating.